1. Field
The embodiment relates to a serial data receiving circuit and a serial data receiving method. More particularly, it relates to a serial data receiving circuit and a serial data receiving method capable of performing interconversion on a bit sequence of data bit groups, between LSB first and MSB first, in serial data transmitted serially in successive data bit groups.
2. Description of Related Art
FIG. 10 is a block diagram of an embodiment of Japanese Patent Publication No. H8-307405. FIG. 10 shows the case that synchronization pattern length is 24 bits and the operation speed is reduced to ⅛ of the bit rate. In FIG. 10, PCM bit serial data is inputted to a shift register 101 and a shift register and latch circuit 102, respectively. The shift register 101 is constituted by 8 bits (1 word), and is adapted to convert bit serial data into 1-word 8-bit word serial data.
The converted word serial data is word-shifted to word latch circuits L101 through L104 arranged in a 4-stage cascade configuration to be sequentially latched with respect to each word. The final stage latch circuit L104 is constituted by 7 bits. Supposing the bits latched in the respective word latch circuits L101 through L104 are denoted in the order b1, b2, b3, . . . , starting from the head bit of latch circuit L104 as shown in FIG. 11, the final bit of the final stage latch circuit L101 becomes b31.
Parallel bits b1 through b31 of all these latch circuits L101 through L104 include 8 frame synchronization patterns (bit combinations) that appear regularly in b1 through b24, b2 through b25, b3 through b26, b4 through b27, b5 through b28, b6 through b29, b7 through b30, and b8 through b31. In consideration of this uncertainty (8 different uncertainties) in Japanese Patent Publication No. H8-307405, 8 frame synchronization parts F101 through F108 are provided so as to correspond to these 8 pairs of patterns, respectively.
The various types of timing signals (latch timing signals, word timing signals, frame timing signals) for the respective frame synchronization parts F101 through F108 are alternatively derived in selector 107 and fed to the next stage circuit such as a shift register and a latch circuit 102. The selector 107 serves to select the timing signals of the frame synchronizing parts (F101 through F108) whose frame synchronization patterns are detected by frame synchronization decision part 105.
Japanese Patent Publication No. H7-221749, Japanese Patent Publication No. H11-145944, Japanese Patent Publication No. 2001-36514, Japanese Patent Publication No. H9-55728 and Japanese Patent Publication No. 2001-308719 disclose examples of other serial data receiving circuits and serial data receiving methods.
While the bit sequence of the serial data inputted to a serial data receiving device is LSB (Least Significant Bit) first, there is case that the bit sequence of word serial data outputted from the serial data receiving device must be MSB (Most Significant Bit) first. Also, on the contrary, while input to the serial data receiving device is carried out by MSB first, there are cases that output from the serial data receiving device must be carried out by LSB first. These exist in various combinations depending on the communication method standards and specifications, standards and the like of the circuit to which the word serial data is to be fed. As a result, there are cases that interconversion on the bit sequence of the serial data, between the LSB first and the MSB first, must be carried out between the input timing and the output timing with respect to the serial data receiving device. However, Japanese Patent Publication No. H8-307405 does not disclose that interconversion is carried out in the serial data receiving device, between the LSB first and the MSB first of serial data. This presents a problem in that it is impossible to accommodate a case that the bit sequence differs between the input timing and the output timing with respect to the serial data receiving device.
In the circuit of Japanese Patent Publication No. H8-307495, selector 107 performs an operation to select a timing signal of the frame synchronization part in which a frame synchronization pattern was detected by a frame synchronization decision part. However, since a specific constitution of the selector 107 is not disclosed, there is a problem that selector 107 cannot be implemented.